1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device comprised of a memory transistor between whose channel formation region and gate electrode are provided, in order from the bottom layer, a bottom insulating film, a charge storing film having a charge storing ability, and a top insulating film, and a method of reading the same.
2. Description of the Related Art
Nonvolatile semiconductor memory transistors are roughly divided into floating gate (FG) types with charge storing means for storing charges (floating gates) formed planarly contiguous and for example metal-oxide-nitride-oxide semiconductor (MONOS) types with charge storing means (charge traps etc.) formed planarly discrete.
An FG type nonvolatile semiconductor memory transistor is comprised of a semiconductor substrate or well over which a bottom insulating film, a floating gate (FG) comprised of polycrystalline silicon etc., a top insulating film comprised of an oxide-nitride-oxide (ONO) film etc., and a control gate are successively stacked.
A MONOS type nonvolatile semiconductor memory transistor is comprised of a semiconductor substrate or well over which a bottom insulating film, a nitride film mainly for charge storage [SixNy (0<x<1, 0<y<1)], a top insulating film, and a gate electrode are successively stacked.
A MONOS type nonvolatile semiconductor memory transistor has carrier traps serving as the charge storing means extending discretely spatially, that is, in the planar direction and thickness direction, inside of the nitride film or near the interface of the top insulating film and the nitride film. Therefore, its charge retention characteristic depends not only on the thickness of the bottom insulating film, but also the energy and spatial distribution of charges trapped by the carrier traps in the nitride film.
When the bottom insulating film has a local leakage current path due to a defect, with an FG type memory transistor, most of the stored charges will pass through the leakage path and leak out to the substrate side, so the charge retention characteristic will easily deteriorate. On the other hand, with a MONOS type memory transistor, since the charge storing means are spatially discrete, only the locally stored charges near the leakage path will pass through the leakage path and locally leak out, so the charge retention characteristic of the entire memory transistor will not easily deteriorate. Therefore, a MONOS type memory transistor will not suffer from as serious a problem of degradation of the charge retention characteristic due to making the bottom insulating film thinner compared with an FG type memory transistor.
As a leading example of an FG type one-memory transistor cell, the ETOX (EEPROM tunnel oxide) cell of Intel Corporation has been known. As a method of arraying ETOX cells, a common source type memory cell array sharing a source has been adopted.
A MONOS type one-memory transistor cell is being closely looked at from the viewpoints of its ability to reduce the cell area and ease of reduction of the voltage. As the typical example thereof, a high density memory cell is known called an “NROM (nitride read only memory) of Saifun Semiconductors, Ltd. An NROM cell utilizes discrete carrier traps as charge storing means, so it can store two bits of data per cell by injecting charges into different regions in the cell. With the method for arraying NROM cells, the virtual ground array method is adopted where cells adjoining each other in a row direction are made to share an impurity diffusion layer and the function of the impurity diffusion layer is used by switching between the source and drain when storing or reading out two bits of data.
As a method of reading an NROM cell, the method is known of reversing the directions of application voltages at the source and the drain from the directions at the time of the write operation, that is, the “reverse read” method. This is disclosed in U.S. Pat. No. 5,768,192.
The above patent describing the reverse read method discloses a MONOS type transistor formed with a trapping layer sandwiched between two silicon dioxide films between silicon formed with a channel and a gate electrode.
In production of a MONOS type memory transistor, when depositing a nitride film by chemical vapor deposition (CVD) over the bottom insulating film formed by silicon dioxide, a time delay (so-called “incubation time”) occurs while forming the film. This is a phenomenon where, for a short while after the start of film formation, time is spent for growing nuclei and almost no film is formed and, after the elapse of a certain time, the film formation rate rapidly increases. The incubation time varies due to the degree of washing and condition of the underlayer and the film formation conditions. An ONO film cannot be formed with good control if incubation time occurs.
If the temperature of forming the nitride film is low, the incubation time tends to become longer when forming the film. However, when forming a MONOS transistor having a gate length of no more than 0.25 μm, the nitride film has to be formed at no more than 800° C. so as to decrease the thermal stress of the entire process. Therefore, in the process of production of a fine MONOS transistor, where the temperature of formation of the nitride film cannot be made too high, the incubation time cannot be decreased.
The above reverse read method enables a high sensitivity read operation with a small charge and therefore is suitable for decreasing the voltage applied in a read operation.
However, if incubation time occurs when depositing a charge storing film (nitride film), in view of the fact that the time will vary, the minimum thickness of the charge storing film has to be able to be secured by making the center of the thickness setting greater than an ideal case without any incubation time. Therefore, the formed charge storing film tends to be thicker than necessary. This becomes a factor obstructing the reduction of voltage by the reverse read method. That is, if the charge storing film is thicker than necessary, the gate voltage cannot be reduced and the low voltage read operation by the reverse read method is no longer possible.
As MONOS transistors are further miniaturized, it will be further necessary to scale down the read voltage correspondingly, but there are limits to the reduction of the read voltage with just the employment of the reverse read method. Therefore, a MONOS memory transistor having a new structure able to further reduce the voltage is earnestly desired.